1. Field of the Invention
The present invention relates to a process for fabricating a thin-film device such as a substrate, including thin-film transistors, of, for example, a liquid crystal panel. The present invention also relates to a thin-film device.
2. Description of the Related Art
In recent years, there have been proposed advanced liquid crystal panels having active matrix drives. A liquid crystal panel includes a liquid crystal filled between a pair of opposing substrates, one substrate being provided with a transparent common electrode and the other substrate being provided with a plurality of small pixel electrodes. The latter substrate includes pixel electrodes as well as gate bus lines, drain bus lines and thin-film transistors.
In producing the substrate including thin-film transistors, gate bus lines, gate electrodes and storage capacitor electrodes are formed on an insulating substrate, the gate bus lines are covered with an insulating layer, a semiconductor layer is formed thereon, and a channel protection film is formed thereon and is covered with an insulating layer. Thereafter, source electrodes, drain electrodes and drain bus lines are formed. Then, an insulating layer is formed thereon, and pixel electrodes are formed thereon. The insulating layer is perforated to connect the pixel electrodes to the source electrodes. In the substrate including thinfilm transistors as described above, the gate bus lines, drain bus lines, thin-film transistors, pixel electrodes and the like are formed by laminating conducting layers and insulating layers.
The liquid crystal panel is required to have a high resolution and a high opening degree of apertures. For this purpose, it is requested that the gate bus lines, the gate electrodes and the like electrically connected to the gate bus lines be densely arranged; this in turn requires that the gate bus lines should be formed narrower and have reduced resistance. To maintain the high quality of the display, furthermore, storage capacitor electrodes are formed on the substrate using the same layer as the gate bus lines. A parasitic capacitance appears between a gate electrode and a source electrode which are overlapping. To maintain a high quality of the display the value of such a parasitic capacitance must be decreased. Also, high yields must be ensured while satisfying these requirements.
The liquid crystal panel is used not only as a display for information equipment but also used in a PDA, in a view finder, in a projector and in the like. The liquid crystal panels are relatively small in size, but it has been desired to provide a liquid crystal panel which is lighter in weight and has higher definition. In these liquid crystal panels, it has recently become necessary to employ low-temperature polycrystalline silicon thin-film transistors that can be formed integrally with the driver.
In order to satisfy both the requirements for narrower bus lines and for lower resistance, it has become necessary to decrease the width of the bus lines and to increase the thickness (or height) of the bus lines. When the thickness of the gate bus lines formed on the substrate is increased, however, the drain bus lines are sharply bent at positions where they are superposed on the gate bus lines when the drain bus lines are formed overlapped on the gate bus lines via an insulating layer. Therefore, the height of the drain bus lines changes at positions corresponding to the upper side edges of the gate bus lines and the etching residue remains; so the drain bus lines are apt to be cut or become defective.
In order to prevent the change in the height of the drain bus lines which may especially occur when the thickness of the gate bus lines is increased, or to prevent the etching residue from remaining unremoved, it is desired to incline the side surfaces of the gate bus lines with respect to the substrate, so that the upper side edges of the gate bus lines become smooth and the drain bus lines are gently bent.
When the gate bus lines are formed by isotropic etching which is normary adopted, however, the upper side edges of the gate bus lines do not become smooth. The inventors of the present case have discovered that the inclination of the side surfaces of all gate bus lines can be controlled to within a predetermined range of angle, by optimizing the baking temperature of the mask and the over-etching time. Upon inclining the side surfaces of the gate bus lines, the upper side edges of the gate bus lines become smooth, so the drain bus lines formed thereon are not broken, and dot defects can be eliminated.
In the etching condition by which the side surfaces of the gate bus lines are to be inclined, however, the angle of inclination of the side surfaces of the gate bus lines varies due to reaction gases generated during the etching, deteriorated etching solutions and variation in the temperature along the surface of the mask when baking the mask. The variation of the angle of inclination of the side surfaces of the gate bus lines can usually be tolerated, but some gate bus lines become too narrow or the angle of inclination is too small so that the side surfaces extend, in the shape of a hem of a skirt, along the substrate. The same also occurs for the gate electrodes and the storage capacitor electrodes formed together with the gate bus lines.
If the angle of inclination of the side surfaces of the gate bus lines is too small and the side surfaces are extended like the hems of skirts along the substrate, the areas of the gate bus lines located close to the substrate are increased and come into contact with other neighboring gate bus lines or gate electrodes, giving rise to the occurrence of short-circuiting in the same layer and causing the source electrodes, drain electrodes and gate electrodes to be overlapped on the gate bus lines to an excess degree, resulting in an increase in parasitic capacitances. In addition, when the channel protection film is to be formed by back-surface exposure using the gate, the shape of the channel protection film often becomes abnormal corresponding to the shape of the gate. As a result of investigation, it has been found that etching defects occur at the region where the gate bus lines, and gate electrodes and gate terminal-drawing portions electrically connected to the gate bus lines are densely arranged.
In the liquid crystal display device, furthermore, it is desired that the wiring is formed of, for example, aluminum or a metal material containing aluminum as a chief component in order to decrease the resistance of the bus lines. Such a metal material is layered on the glass substrate by, for example, sputtering and then patterned into a predetermined shape by etching or the like. However, unless the degree of vacuum is sufficiently high in the sputtering chamber prior to forming the films, aluminum or a metal containing aluminum as a chief component is apt to form bumps due to the subsequent thermal hysteresis, resulting in destruction of devices formed on the aluminum bus lines.
Moreover, a polycrystalline silicon thin-film transistor (p-SiTFT) has a mobility about 100 times as great as that of an amorphous silicon thin-film transistor (a-SiTFT), and makes it possible to form peripheral circuits and very small TFTs, which makes it possible to fabricate a liquid crystal panel that could not be achieved with the a-SiTFTs. However, the p-SiTFT has a high ON current value and a high OFF current value, permitting a large current leakage. Therefore, dot defects may occur after the panel is fabricated, and the peripheral circuits formed using p-SiTFTs consume large amounts of electric power.
In order to reduce the OFF current value therefore, it has been proposed to form an offset around the gate using an LDD (lightly doped drain) structure. For example, the channel portion in the semiconductor layer is not doped with impurities but the portions on the outer side of the channel portion in the semiconductor layer are doped with impurities to form an HDD (heavily doped drain) to form a source electrode and a drain electrode. Here, small regions between the channel portions and source electrode/drain electrodes are doped with impurities to a smaller degree than in the portions of the source electrode and the drain electrode, to thereby form the LDD, i.e., to form an offset.
Japanese Unexamined Patent Publication (Kokai) No. 7-235680 discloses a method for fabricating a thin-film transistor in which an offset is formed. This method includes the steps of forming a semiconductor layer on an insulating substrate, forming a gate electrode having a broad bottom surface (having inclined side surfaces) on the semiconductor layer, doping the semiconductor layer with impurities using the gate electrode as a mask, and etching the inclined side surfaces. A thick portion of the gate electrode does not permit impurities to pass therethrough but the inclined side surfaces of the gate electrode permit impurities to pass therethrough a little. Therefore, the portions covered by the inclined side surfaces of the gate electrode in the semiconductor layer form the LDD, i.e., the offset. According to this prior art, however, the gate electrode must be formed of a material that permits impurities to pass therethrough. According to the production method of this prior art, therefore, limitation is imposed on the materials that can be used as the gate electrodes; i.e., it is not allowed to use aluminum or the like metal which is most adapted to form gate electrodes and gate bus lines. Besides, impurities may pass through the thick portion of the gate electrode, deteriorating the performance of the channel.